1. Field of the Invention
The present invention relates to a semicustom integrated circuit (IC or LSI) such as an ECL (Emitter Coupled Logic) gate array, and more particularly to a wiring structure of a source line used in a semicustom integrated circuit.
2. Description of the Related Art
An ECL gate array is disclosed in, for example, Satoh et al., "A 209K-Transistor ECL Gate Array with RAM", IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 24, No. 5 October 1989 pp. 1275-1279. In the conventional ECL gate array disclosed in this document, pads are arranged on peripheral portions of a chip; e.g., along the four sides of the chip. Peripheral circuit cells are arranged at regular pitch on part of the chip to the inside of the pads, while an internal circuit is formed on a part to the inside of the peripheral circuit cells. As an example of the peripheral circuit cells, input/output circuit cells of ECL level is formed along two opposed sides of the chip and input/output circuit cells of TTL (transistor transistor logic) level is formed along the other two opposed sides of the chip. Alternatively, peripheral circuit cells may be arranged as follows:
Input/output circuit cells of ECL level are arranged along the two opposed sides of the chip. Input/output circuit cells of ECL level and input/output circuit cells of TTL level are arranged along one of the other two opposed sides of the chip, and selectively used, thereby enabling either an ECL level signal or a TTL level signal to be input or output. Input/output circuit cells of ECL level are arranged along the other of the two opposed sides. In the conventional ECL gate array as described above, the number and positions of ECL level and TTL level input/output circuit cells are determined in advance. In addition, both the number of input/output circuit cells for selectively inputting and outputting an ECL level signal and a TTL level signal and the positions thereof are limited. For this reason, the internal circuit and the peripheral circuit cells cannot be wired in an optimal manner, with the result that the performance of the ECL gate array is lowered--for example, the operation speed is reduced or skew is increased. Consequently, improvement of utility, which is an advantage of the gate array, is restricted.
The above problem is not confined to an ECL gate array but arises also in a semicustom integrated circuit such as a MOS gate (insulating gate) array and a standard cell type LSI.